Measurement Technology for Semiconductor Test
Measurement time correlation of CTIA design enables plot of period vs. time. This enables us to easily distinguish between random jitter and systematic jitter in a signal (notice the 6 distinct PERIOD values caused by a ground loop problem between the PLL divider and VCO).
Many of the latest high-speed interfaces like LVDS and DVI/TMDS are “source synchronous” buses that transmit a clock signal synchronous to the data transmitted, but asynchronous to the rest of the device operation. The unpredictability of source synchronous bus output phase makes it difficult to perform functional test since the placement of digital comparator strobes cannot be predefined. Typical work-arounds to overcome phase unpredictability include “pattern sync,” “bit-align,” or “pattern match-mode.”
These measurement synchronization techniques normally involve time-consuming comparison searches to determine bus out-put phase by shifting a known pattern until its phase aligns with the phase of a matching bit sequence in the test signal. Thanks to GuideTech’s CTIA technology, this no longer has to be the case.
Unlike more traditional time counter instruments that start/stop a counter between measured edges (but don’t maintain timing relationships between measurements), CTIA technology is based on a “time tagging” technique that continuously captures and stores edge event timing relative to the start of a series of measured events.
Instruments without time correlation have difficulty measuring long-term and deterministic anomolies and often must use complex algorithms to estimate the different components of jitter in a device signal. The power of CTIA technology is that, like an oscilliscope, CTIA instruments allow engineers to see what is actually happening to a signal over time very clearly.
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