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PLL Testing Using the Femto
Continuous Time Interval Analyzer
Introduction:
Integrated circuit testing is becoming
ever more complicated with increasing clock rates,
lower timing margins and the proliferation of on-board
phase locked loops (PLL's). With this in mind, Guide
Technology has introduced the Femto Continuous Time
Interval Analyzer (CTIA), a new concept in time measurement
instrumentation. Much faster than previously available
time measurement instrumentation, the Femto features
truly parallel measurements, rapid time-correlated
measurement rates, and multiple Digital Signal Processor
(DSP) processing power. The Femto can test a wide
variety of PLL circuits with a maximum frequency of
over 800 MHz. PLL measurements such as frequency and
jitter can typically be accomplished in 100 milliseconds
for 64 points. The Femto frequency measurement features
typical accuracy of 1 part per million (ppm). The
Femto can also make extremely precise jitter measurements
with a jitter noise floor of +/- 3 picoseconds. NOTE:
The programming details in this application note
apply to the Femto 2000. Please refer to the User Manual
for Femto 3200 implementation.
What Is the Femto ? The Femto is a true Continuous
Time Interval Analyzer (CTIA), unlike many timing instruments
which are merely frequency or time counters. The Femto
can be used in either stand-alone mode or integrated
into a production test environment. Front Panel Operation
The Femto is accurate enough to be used as a high precision
lab instrument. Operation in lab instrument mode is
from the front panel using a mouse and keyboard for
user input. The Femto includes a large display screen
on its front panel for easy data and graphics display.
Production Oriented Design/Operation The Femto design
is optimized for high-throughput testing in an automated
test equipment (ATE) environment. The Femto can take
measurements on up to 8 channels simultaneously. Rapid
and powerful measurement calculations are processed
by up to 4 on-board digital signal processors (DSP's).
Control of the instrument in production mode is via
a GPIB interface.
Configuration:
With A Tester The Femto
has been configured to work with virtually any ATE
system currently in use. Instrument control and data
transfer is via GPIB interface. Programming is accomplished
using the industry standard "C" programming
language and custom, high level device driver calls.
Femto driver code is available for both Unix and Windows
platforms. Typical ATE Setup Loadboard Interface A
key part of any ATE application is the loadboard signal
interface by which the Device Under Test (DUT) signals
to be sent to the Femto . Guide Technology provides
several choices for loadboard signal interfaces. The
loadboard interface can be via a pogo block connector
mounted in the testhead, GT QuikConnect connectors
mounted on the loadboard and testhead or traditional
SMA connectors mounted on the loadboard. The signals
are sent from the loadboard interface connectors to
the Femto via high-bandwidth coax cables. PLL Measurements
In Production Definition of Phase-Locked Loop (PLL)
A phase-locked loop (PLL) is a circuit that synchronizes
the phase of a locally generated signal with that of
an external signal in any electronic system. Examples
of PLL applications 1. Skew & clock delay control
in large digital systems 2. Frequency shift correction
in satellite transmissions 3. Local & reference
oscillator locking in analog video equipment.
A phase detector is used
to determine the phase difference between an external
reference signal (Fextern) and a local signal (Flocal).
The Flocal signal is generated by an on-board Voltage
Controlled Oscillator (VCO). Since the phase detector
circuit requires that the two comparison signals
be of the same frequency, a "divide-by-N" circuit
is inserted between the VCO output (Flocal) and the
phase detect circuit so that the two signals are at
the same frequency for proper phase comparison in the
phase detector. The voltage produced by the phase detector
(Vph_diff) represents the difference in phase between
the two signals being phase-locked. This phase difference
voltage (Vph_diff) is filtered by a Loop Filter to
remove any high frequency noise (ripple) and then fed
into the voltage controlled oscillator (VCO) - the
same VCO which is used to generate the Flocal signal
and which adjusts Flocal to match the phase of Fextern
using the Vph_diff signal. Common PLL Measurements
The two most common PLL measurements tested are Average
Frequency and Timing Jitter.
Average Frequency The Average Frequency Measurement
determines how close the PLL output frequency is to
the desired frequency. Several different types of frequency
measurements are possible with various trade-offs of
accuracy and test time. Frequency measurements are
discussed in more detail later in this application
note. Jitter Timing Jitter is a measurement of how
much the PLL output frequency or output period varies
from the desired value. Of particular concern are PLL's
in digital systems which face constraints on the variation
allowed in the length of individual output periods.
RMS Jitter Cycle jitter is determined by taking many
measurements of the PLL output period. The Femto on-board
DSP's can quickly calculate standard deviation of these
output single period measurements. The standard deviation
value is equal to the RMS jitter of the output clock.
If the distribution of the single period measurements
is Gaussian then the cycle jitter is considered random
and the RMS jitter can be used to project the range
of the jitter present. Peak to Peak Jitter Peak to
Peak Jitter is determined by the range of the single
period measurements in the measurement block. The Femto
on-board DSP's can also quickly calculate the minimum
and maximum periods that were measured. The Peak to
Peak jitter measurement is the difference of the maximum
and minimum measured periods. Peak to Peak Jitter measurement
is described in more detail later in this application
note. RMS Jitter vs. Peak to Peak Jitter The Peak to
Peak jitter measurement is an actual measurement of
the range of the single periods present while the RMS
jitter is used to project the range of the single periods
that will be present.
The advantage of the RMS
jitter measurement is that the RMS value can be established
after a comparatively few single period measurements
(typically 50 or more) while Peak to Peak jitter
measurement will continue to increase as more and
more periods are measured (stabilizing somewhat after
perhaps thousands of single period measurements).
Long Term Jitter The Long Term Jitter measures cycle
jitter as well as low speed frequency variations (frequency
drift) that will not be show in the previously described
cycle jitter measurements. Long Term jitter uses a
special Femto mode called Time Interval Error (TIE)
Mode. The Long Term Jitter measurement is described
in more detail later in this application note. How
Does Femto Make Timing Measurements? An extensive description
of the Femto many modes and features is beyond the
scope of this application note. However, some knowledge
of the Femto operation is helpful. The Femto is capable
of many types of measurements. Continuous, Time-correlated
Timing Measurements The Femto CTIA makes direct measurements
of event timing triggered by user-defined edge polarity
and threshold voltage. Every edge measured by the Femto
CTIA is "time stamped" with two pieces of information:
the time Tn and the event En relative to the time stamp
(T0, E0) of the first edge measured in a set of measurements.
That is, every edge timing measured in a signal stream
is correlated in time relative to the first edge timing
measured, T0, in a set of measurements. Every event
measured in a signal stream is correlated in time relative
to the first event counted, E0, in a set of measurements
The easiest type of measurement to understand is the
two-edge measurement such as Single Period or Pulse
Width. The Femto takes the specified measurement, records
the measurement, records the time at which the measurement
occurred and records the event count of the measurement.
This constitutes a single measurement. An example of
a single edge measurement is the frequency measurement.
The Femto records the time at which the edge occurred
and records the event count of the measurement. The
frequency measurement is calculated by subtracting
the time of the previous edge from the time of the
current edge and dividing by the number of edges observed.
Usually a large group of measurements are taken at
one time by repeating either of the preceding processes.
The statistics of the measurement group are then be
calculated by the Femto on-board DSP processors.
These statistics include
the average measurement value, the minimum measurement
value, the maximum measurement value and the standard
deviation of the measurement values. Arming Arming
controls when the each measurement actually occurs.
The Femto supports a wide variety of timing modes
including external arm (take a measurement when an
external signal occurs), arm by time (take measurements
at a specified rate) and arm by time after an external
arm. Voltage Threshold & Polarity A
voltage threshold & edge polarity must be specified
in order for the Femto to make measurements. A measurement
will occur when the input edge crosses the specified
voltage threshold. The voltage threshold can be set
as either a fixed voltage or as a percentage of the
input signal's voltage swing. Statistical vs. Time
Domain Measurements Two techniques are commonly used
to make relevant timing measurements from the block
of measurements gathered by the Femto . The most common
technique is to derive the basic statistics of the
measurement block. The Femto DSP's automatically return
the following statistics for any measurement block:
MEAN (average), MIN (minimum), MAX (maximum) and STD
DEV (standard deviation). A second technique is for
the entire block of measurements to be used instead
of just the standard statistics. The Femto automatically
records the time at which each of the measurements
were taken. Plotting the measurement values vs. the
time when they were taken allows analysis to be done
in the time domain. The following is a comparison of
statistical and time-domain test techniques: PLL Statistical
Measurements The Femto typically measures a timing
parameter by first making a large group of measurements.
The user then has the option of having the statistics
calculated for that group of measurements or having
all of the measurements returned to the tester. If
just the statistics are needed, the of measurements
are processed by the on-board DSP's. The statistics
of the group are returned to the tester. The DSP-derived
statistics automatically calculated and returned to
the tester are the mean (average) of the group of measurements,
the minimum measurement of the group, the maximum measurement
of the group, and the standard deviation (RMS) of the
group. The tester then makes a pass/fail decision based
on the statistics.
Statistical Analysis Summary:
Step 1: Femto takes a block of time measurements from
the PLL output.
Step 2: Femto calculates the timing statistics from
the block of timing measurements (mean, maximum, minimum,
standard deviation).
Step 3: Timing statistics are transferred to the tester.
Step 4: Tester datalogs and makes pass/fail decisions
based on the timing statistics.
Advantages:
Faster test time because only the statistics are passed
to the tester. Disadvantages: Pass/fail limited to
a few standard statistical measurements. Timing information
may be obscured by statistical process. Time domain
tests not possible. PLL Time-Domain Measurements The
entire group of timing measurements made by the Femto
can be returned to the tester if the standard statistical
analysis is not sufficient. The tester can then make
pass/fail decisions based on time-domain or other analysis
of the raw time measurements. The Femto can also return
the time that each measurement was made along with
the measurement value. Knowing the value of each measurement
and when the measurement was made allows analysis in
the time-domain. The Femto- high measurement rate of
up to 1 Megasample per second allows direct, single-shot
measurement and analysis of PLL performance in the
time domain.
Much of this type of time domain analysis may be missed
using averaging techniques and statistical techniques
common to many other instruments. Measurements that
can be made only in one-shot mode include repeated
variations of the PLL frequency and problems in the
lock acquisition and loop performance of the PLL. Time
domain analysis can be useful in production test programs
where measurements are required which cannot be done
with statistical techniques. Time domain analysis can
also be useful for characterization test programs where
design criteria and device performance are verified
to an extent not required for production. The Femto
can also be used as a bench-type instrument using the
front panel controls and the front panel display to
perform time domain analysis in a debug mode.
Time-Domain Analysis Summary:
Step 1: Femto takes a block of time measurements from
the PLL output.
Step 2: The block of timing measurements are transferred
to the tester.
Step 3: The time domain measurements are calculated
from the block of data.
Step 4: Tester datalogs and makes pass/fail decisions
based on the time domain measurements.
Advantages:
All timing information available to the tester. Time
domain tests are possible. Disadvantages: Slightly
longer test time due to more data being passed. PLL
Measurement Details Introduction We can now review
the details of some of the more common PLL test measurements
being made today. Details for the following measurements
are included in this application note: Statistical
tests: Average Frequency Measurement Single Period
Measurement Frequency Measurement Using Single Period
RMS Jitter Measurement Peak to Peak Jitter Measurement:
Deterministic Jitter Long Term Jitter (Frequency Wander)
Pulse Width Measurement Duty Cycle Calculation Rise
Time / Fall Time Measurements Voltage Related Tests:
Output Level Searches Time Domain Tests: PLL Lock Time
(PLL Settling Time) PLL Loop Filter Bandwidth PLL Frequency
Modulation Test Time Reduction Technique: Multiple
Block Measurement Mode Average Frequency Measurement:
Measuring the Average Frequency is the most basic PLL
test. The FREQUENCY AVERAGE measurement mode provides
the most accurate means of measuring frequency.
First, a time interval is selected (3 us for best
accuracy). The Femto automatically counts number of
signal edges during each time interval. The frequency
is then calculated for each time interval. The Average
Frequency and other statistics of the group of measurements
are returned to the tester.
Step 1: Set up the DUT so that the PLL output is clocking
and stable.
Step 2: Take the PLL output frequency measurements.
MODE = FREQUENCY AVERAGE MEASUREMENT ARM = BY TIME,
1us or greater interval. SAMPLE COUNT = User Specified
Figure 3 - Frequency Average Measurement Mode
Step
3: Read back the Frequency Average statistics and
make PASS/FAIL decision based on the MEAN value. Single
Period Measurement: The SINGLE PERIOD Measurement
mode provides measurements of the time delays of individual
periods in the PLL output. The single period results
can be read back either as the basic statistics (mean,
minimum, maximum and standard deviation) or else
the single period measurements can all be read back
in a block read. The single period measurement statistics
provide enough information for several common tests,
as shown in the following examples. Each individual
period measurement is effectively an instantaneous
frequency measurement. Plotting the single period
measurements vs. time allows time-domain analysis of
the PLL output frequency.
Step 1: Set up the DUT so that the PLL output is clocking
and stable.
Step 2: Take the single
period measurements. MODE = SINGLE PERIOD MEASUREMENT
ARM = BY TIME, 1us or greater interval. SAMPLE COUNT
= User Specified Figure 4 - Single Period Measurement
Mode & Femto- Display
Step 3: Read back the Single Period statistics and
make PASS/FAIL decision based on the MEAN, MIN amd
MAX values. Frequency Measurement Using Single Period:
The average frequency can be calculated from the Single
Period Measurement statistics by inverting the MEAN
(average) period measurement. Test time can be saved
by this method since the FREQUENCY AVERAGE test can
be skipped.
Step 1: Obtain the Single Period MEAN statistic from
the Single Period test..
Step 2: Calculate the Frequency Average MEAN statistic
and make PASS/FAIL decision based on test limits. RMS
Jitter Measurement: The RMS Jitter of a signal can
be calculated by taking the standard deviation of the
Single Period measurement above. Knowing the RMS jitter
is useful because allows calculation of other jitter
statistics if the jitter follows a Gaussian distribution.
Step 1: Obtain the Single Period STD DEV statistic
from the Single Period test. Step 2: Make PASS/FAIL
decision based on the Single Period STD DEV and the
test limits.
Peak to Peak Jitter Measurement:
The Peak to Peak Jitter
of a signal is the total spread of the single period
measurements. The Peak to Peak Jitter is the measured "worst case" jitter.
The Peak to Peak jitter can be calculated by the
computing the range of measurements made in the Single
Period measurement above. The range is the Maximum
Single Period measurement minus the Minimum Single
Period measurement. Note that the Peak to Peak Jitter
measurement will tend to grow as the sample count
grows while the RMS Jitter will tend to stabilize
while the sample count grows.
Step 1: Obtain the Single Period MINIMUM and Single
Period MAXIMUM statistics from the Single Period measurement
above.
Step 2: Calculate the Peak to Peak Jitter using the
following equation: Peak to Peak Jitter = Single Period
MAX - Single Period MIN
Step 3: Make PASS/FAIL decision based on the Peak
to Peak Jitter and the test limits. Deterministic Jitter
Deterministic Jitter is timing jitter that is not random.
Many times Deterministic Jitter is inherent in the
design of a particular PLL. Deterministic Jitter is
often periodic. The PLL design displayed in Figure
5 has periodic Deterministic Jitter due to the PLL
divider stages. Figure 5 is an example of PLL analysis
in the time domain that would not be possible using
statistical or oscilloscope techniques.
Long Term Jitter is the
deviation of the PLL output from an "ideal" clock output over a long period of
time. While Long Term Jitter measures the variations
in individual cycle periods, as does a Single Period
Jitter measurement, a Long Term Jitter measurement
also measures longer term variations in frequency,
also known as frequency wander. The Femto provides
a special measurement mode called Time Interval Error
(TIE) to measure Long Term Jitter. The Time Interval
Error mode reports the time difference between the
measured PLL output edges and an "ideal" edge calculated
from a specified frequency. The TIE mode is used to
measure variation or drift from the ideal clock frequency
and phase as well as to measure short-term cycle jitter.
The TIE results will include the effects of both short
and long term timing error in the PLL output. TIE results
can be read back either as statistics (mean, min, max,
std dev) or the individual timing error measurements
can all be read back in a block read.
TIE results can be affected
by inaccuracy in the "ideal" frequency
specified. The "ideal" frequency is usually the result
from a previous frequency measurement. Care must be
taken that the "Ideal" frequency value used is very
accurate or the TIE errors will grow continuously due
to the mismatch of the "ideal" PLL frequency and the
actual PLL frequency.
Step 1: Determine the PLL
output "ideal" frequency
by using previous frequency measurements.
Step 2: Set up the DUT so that the PLL output is clocking
and stable.
Step 3: Take the TIE measurements. MODE = Time Interval
Error (TIE) SAMPLE COUNT = User Specified MEASUREMENT
ARM = BY TIME, 1us or greater interval Figure 6 - Time
Interval Error (TIE) Measurement Mode
Step 4: Make PASS/FAIL decision based on the Minimum
TIE and Maximum TIE statisitcs and the test limits.
Example: Frequency Wander The TIE measurement selects
certain edges of an input signal, records the transition
times of those edges, and subtracts from those times
the corresponding transition times of an ideal signal
of the same frequency. The resulting series of numbers,
called time interval errors, or TIEs, indicate how
far each of the measured edges is from its ideal position.
A positive TIE indicates that the corresponding input
signal transition lags its ideal position.
A negative TIE indicates that the corresponding input
signal transition leads its ideal position. The minimum
and maximum TIE measurements represent the amount of
long-term jitter (wander) in the PLL output. Pulse
Width Measurement: The PULSE WIDTH Measurement mode
measures either the width of the positive going pulse
(Pulse Width High) or the width of the negative going
pulse (Pulse Width Low). The PULSE WIDTH Measurement
mode provides a block of measurements, as did the Single
Period test earlier. Reading back the Femto DSP generated
statistics can provide the average pulse width (mean),
the smallest pulse width measured (minimum), the largest
pulse width measured (maximum) and the pulse width
jitter (standard deviation). As with other tests, the
pulse width results can all be read back in a block
read also. Unlike the Frequency and Single Periods
measurements,
Pulse Width measurements can be influenced strongly
by the voltage threshold setting and also by signal
distortion. This is because the Pulse Width test measures
edges of opposite polarities (rise to fall or fall
to rise) so that pulse slew rates and distortion can
add or subtract from the reading. Frequency and Single
Pulse measurements are made on edges of the same polarity
(rise to rise or fall to fall) as so slew rates and
signal distortion on one edge tend to offset the same
problems on the second edge.
Pulse Width High Measurement:
Step 1: Set up the DUT so that the PLL output is clocking
and stable.
Step 2: Take the Pulse Width High measurements. MODE
= PULSE WIDTH HIGH MEASUREMENT ARM = BY TIME, 1us or
greater interval. SAMPLE COUNT = User Specified THRESHOLD
= FIXED or PERCENTAGE
Step 3: Read back the Single Period statistics and
make PASS/FAIL decision based on the MEAN, MIN, MAX
and STD DEV values. Figure 7 - Pulse Width Measurement
Mode Pulse Width Low Measurement:
Step 1: Repeat the Pulse Width High test using Pulse
Width Low mode. MODE = PULSE WIDTH LOW Duty Cycle Calculation:
The clock Duty Cycle is the ratio of the Mean Pulse
Width High to the Mean Single Period as in Equation
1 below. Like Pulse Width measurements, Duty Cycle
measurements can be affected by threshold settings
and signal distortion.
Step 1: Calculate Duty Cycle using the following equation:
Equation 1: Calculate the PLL Duty Cycle using the
pulse width high and single period measurements. MEAN
of Pulse Width High Duty Cycle = ---------------------------------------
MEAN of Single Period
Step 2: Make PASS/FAIL decision based on the calculated
Duty Cycle value. Rise Time / Fall Time Measurements:
The RISE TIME Measurement mode provides measurements
of the rise time delay between two different voltage
thresholds on the same rising signal edge. The FALL
TIME Measurement mode does the same for the fall time
delay between two different voltage thresholds on the
same falling signal edge. Typically only the MEAN rise
and fall time statistics are used for test purposes.
Rise Time and Fall Time measurements use both a lower
and an upper voltage threshold setting. These two voltage
threshold settings can be programmed either as fixed
voltage levels or as percentages of the overall voltage
swing. Rise Time and Fall Time measurements can be
influenced strongly by incorrect voltage threshold
settings and also by signal distortion.
Step 1: Set up the DUT so that the PLL output is clocking
and stable.
Step 2: Take the Rise Time (or Fall Time) measurements.
MODE = RISE TIME (or FALL TIME) MEASUREMENT ARM = BY
TIME, 1us or greater interval SAMPLE COUNT = User Specified
LOWER THRESHOLD = FIXED or PERCENTAGE UPPER THRESHOLD
= FIXED or PERCENTAGE
Step 3: Make PASS/FAIL decision based on the Mean
Rise Time measurement (or Mean Fall Time measurement)
and the test limits. Risetime Measurement Mode Output
Level Searches The Femto provides a high-speed, automated
routine to determine the maximum and minimum voltages
found in an input waveform. The results of the voltage
searches can be used to test the PLL output VOL and
VOH levels. The search results can also be used to
set voltage thresholds to a percentage of the voltage
swing. The voltage search routine typically executes
in 100 milliseconds or less for 8 channels.
PLL Lock Time (PLL Settling
Time): The time it takes for a PLL to adjust to a
new frequency setting is called the PLL "lock time" or "settling time". The PLL lock
time can be critical in many applications where changes
to the PLL output frequency must be stabilized quickly.
Important PLL performance information can be obtained
by watching the PLL response as it acquires lock. The
Femto can perform two different kinds of lock time
tests. A "go/nogo" lock time test simply tests whether
lock has been acquired at the specified time. A "time-to-lock" test
measures the actual lock time for the PLL. The "time-to-lock" measurement
test provides all of the single period measurements
as the PLL adjusts and locks. In a debug environment,
the Femto single period measurements can be examined
graphically from the front panel or can be read and
processed as a block of measurements. PLL Lock Time
("Go/NoGo" Test Method): The PLL "Go / NoGo" Lock Time
test simply measures the PLL output frequency after
the specified lock time. The device passes if the measured
frequency is in the specified frequency range.
Step 1: Set up the DUT so that the PLL output is in
its initial condition.
Step 2: Setup the Femto to take the measurements MODE
= FREQUENCY AVERAGE MEASUREMENT ARM = BY TIME, 1us
interval BLOCK ARM = EXTERNAL SAMPLE COUNT = User Specified
Step 3: Begin the PLL Lock
sequence by programming the programming the PLL or
changing its input frequency. An EXTERNAL ARM is
sent after the specified PLL settling time. The External
Arm signals the Femto to begin measuring the PLL
output frequency. Figure 9 - External Arming of Frequency
Average Measurement Step 4: Verify that the MEAN
statistics value of the FREQUENCY AVERAGE measurement
is within the test limits for the PLL output frequency.
PLL Lock Time ("Time-to-Lock" Measurement
Method): The PLL Lock Time "time-to-lock" measurement
test finds the actual time when the PLL acquired lock.
This test is performed with the Femto in single period
measurement mode. As mentioned previously, each single
period measurement is actually an instantaneous frequency
measurement. The block of data obtained by the test
program is the actual instantaneous frequency measurements
as the PLL acquired lock. Measurements are made at
the maximum rate of 1 MHz (1 us intervals).
Step 1: Set up the DUT so that the PLL output is in
its initial condition.
Step 2: Setup the Femto
to take the measurements MODE = SINGLE PERIOD MEASUREMENT
ARM = BY TIME, 1us interval BLOCK ARM = EXTERNAL
SAMPLE COUNT = User Specified Figure 10 - PLL "TIME-to-Lock" Measurement
Step 3: The blocks of single-period data and associated
elapsed-time data are read back to the tester after
the measurement has been completed.
Step 4: The test program calculates the lock time
by examining the data block and determining when the
measured frequency entered the specified lock range.
Step 5: If desired, the
PLL frequency can be plotted against the elapsed
time to provide a complete picture of the PLL lock
response. PLL Loop Filter Bandwidth: The speed with
which a PLL reacts to frequency and phase errors
is called the PLL Loop response. The PLL Loop Response
is determined largely by the PLL Loop Bandwidth.
The PLL Loop Bandwidth is therefore an important
parameter in determining PLL performance. Too little
bandwidth results in a PLL that is slow to lock to
a new frequency. Too much bandwidth will result in
a PLL which is quick to move to a new frequency but
which may tend to oscillate, may over-shoot the desired
frequency and may pass input jitter to the output.
Standard statistical analysis of the PLL frequency
and jitter cannot be used to measure the PLL loop performance.
Statistical analysis of a PLL with poor loop performance
may indicate a poor jitter performance but there is
no way to use statistical analysis to determine the
PLL loop performance. Time domain analysis can be used
to not only measure the loop bandwidth but to also
graph the loop response, including over-shoot and under-shoot.
PLL loop bandwidth is tested by applying a phase shift
to the input signal of the PLL. The phase shift can
often take the form of a skipped input clock. The phase
shift of the input clock causes the PLL to adjust (phase-lock)
to the new input phase. The speed at which the PLL
phase-locks to the new input phase is a measure of
the PLL's loop response and loop bandwidth. Time Interval
Error (TIE) mode is used in this measurement. In TIE
mode, change in the PLL output phase is measured as
a phase error relative to an "ideal" output clock.
Step 1: Determine the PLL
output "ideal" frequency
by using previous frequency measurements.
Step 2: Set up the test vectors to provide an external
arm after the PLL output is clocking and stable.
Step 3: Set the test vectors to provide a input phase
shift or skipped input clock shortly after the external
arm.
Step 4: Take the TIE measurements. MODE = Time Interval
Error (TIE) SAMPLE COUNT = User Specified MEASUREMENT
ARM = BY TIME, 1us or greater interval BLOCK ARM =
External Arm Step 5: Continue measurements until the
PLL output has completed its phase adjustment. Figure
11 - Example of phase shift applied to PLL input signal
Step 6: Calculate the total bandwidth of the PLL output
using the following equation: PLL Loop Bandwidth =
0.35 / risetime where risetime is the time it took
for the PLL to settle to the value of the induced phase
shift error from the time the input signal was phase
shifted (e.g. 50ns). Figure 12 - Graph of Time Interval
Error (TIE) measurements indicating time for PLL to
lock onto applied input phase shift PLL Frequency Modulation:
PLL Frequency Modulation occurs when the PLL output
frequency varies over time. PLL modulation can be deliberate,
such as spread spectrum applications, or it can be
accidental, which results in poor jitter performance.
PLL Modulation is difficult to measure statistically
beyond simply finding that the PLL output has excessive
jitter. The Femto front panel display can often display
PLL modulation in the time domain.
The statistical information includes a large standard
deviation (jitter) but there is no indication as to
the cause of the jitter. The histogram is more informative
than the raw statistic numbers but again it gives no
indication of why the measured frequency range is so
large. The upper left diagram (red) of Figure 13 plots
the time domain information of PLL output frequency
versus time. The effect of modulation is clearly shown
as the measured frequency rises and falls over time.
This type of modulation is not observable when the
timing information is reduced to the standard statistics.
The effect of modulation
is clearly seen as the measured frequency rises and
falls over time. This type of modulation is not observable
when the timing information is reduced to the standard
statistics. The DSP's can process the multiple blocks
simultaneously and the multiple results are transferred
to the tester in a single transfer. Test time can
reduced by as much as 50% in some cases. Multiple
Block mode can be illustrated by the case where a
PLL's output frequency and RMS jitter are to be measured
at three different VDD voltages. The conventional
technique would be to repeat the measurement three
different times and the total test time would be three
times as long as a single VDD measurement. Multiple
block mode can be used to capture the measurements
of the three VDD levels in three sequential blocks,
with only the VDD settling time between the captures.
The three blocks are DSP processed in one operation
and the results are transferred to the test in one
transfer. Total test time is about 50% longer than
for a single VDD. Femto PLL Shell Program The Guide
Technology staff of applications engineers has developed
a "Shell Program" to aid customers in developing their
PLL test programs. The Shell Program is designed so
that the user can get most of the standard PLL tests
running quickly by simply enabling flags and setting
variables in the definition file. The Shell Program
was also designed to run on many different testers
through the ATE-specific "User Function" capability.
Benchmarks NOTE: These test times are based on Femto
2000 measurements taken in March 2002. Major throughput
enhancements have been implemented since that improve
these times by a factor of two or more.
Benchmark #1
Conditions: 8 parallel PLL channels 64 samples per
measurement Test suite performed: VOL/VOH search Frequency
Average Single Period Average Single Period RMS Jitter
Single Period Peak to Peak Jitter Pulse Width Pulse
Width RMS Jitter Rise Time Fall Time Approximate Test
Time: 330 milliseconds
Benchmark #2
Conditions: 2 parallel PLL channels 400 samples Tests
run at 3 VDD levels Test suite performed: Frequency
Average Single Period RMS Jitter Approximate Test Time:
150 milliseconds.
Benchmark #3
Conditions: 2 parallel PLL channels Test suite performed:
PLL Lock Time Measurement Results: Measured PLL 1 Lock
Time: 40 microseconds Measured PLL 2 Lock Time: 45
microseconds Approximate Test Time: 45 milliseconds
Benchmark #4 Conditions: 2 parallel
PLL channels Test suite performed: PLL Loop Bandwidth
Measurement Results: Measured PLL 1 Loop Bandwidth:
72 KHz Measured PLL 2 Loop Bandwidth: 45 KHz Approximate
Test Time: 40 milliseconds
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